The present invention relates to a phase comparator circuit suited for a phase locked loop, and more particularly to a phase comparator circuit adapted to implemented by a semiconductor integrated circuit.
Recently, phase locked loop (hereinafter abridged as PLL) technology has been frequently used in a frequency synthesizers, demodulator circuits or the like in the field of electronic communication. The PLL technology relates to a technology which generates a signal in synchronism with a reference frequency or a multiple thereof of a reference signal. Taking an example of the frequency synthesizer, a basic configuration of the PLL technology is explained below.
A PLL circuit comprises a phase comparator circuit which receives a reference signal at one input terminal, a low-pass filter which permit the output of the phase comparator circuit to pass therethrough, a voltage controlled oscillator (hereinafter abridged as VCO) which is controlled by the output of the phase comparator circuit passed through the low-pass filter and a frequency divider which frequency-divides the output of the VCO by a factor of N and applies the frequency-divided output to the other input terminal of the phase comparator circuit. The output signal having a frequency fv from the frequency divider is phase-compared with the reference signal having a frequency fr applied to the phase comparator circuit, which produces an output voltage indicative of a phase difference. If the polarity of the output voltage of the phase comparator is selected such that it lowers an oscillation frequency fo of the VCO when the phase of the output signal of the frequency divider is leading relative to the phase of the reference signal, the phase of the output signal of the frequency divider gradually leads relative to the phase of the reference signal when fv is higher than fr so that the oscillation frequency fo and hence fv=fo/N are lowered. When the frequency fv of the output signal of the frequency divider exactly coincides with the frequency fr of the reference signal, the circuit assumes a stable state with a phase difference being such that the phase comparator produces a control voltage necessary to keep a free running frequency fo' of the VCO at fo (=N.multidot.fr). In this manner, the output of the VCO produces a signal having a frequency which is exactly N times as high as the frequency of the reference signal.
The phase comparator circuit frequently used in the PLL may be a sample and hold circuit combined with a waveform converter circuit for converting the signal to be phase-compared to a sawtooth wave, a ramp wave or the like. An example of an integrated circuit implementation of such circuit is shown in FIG. 1, in which numeral 10 denotes a waveform converter circuit for converting the signal to be phase-compared with the reference signal to the sawtooth wave. The signal to be compared, which is applied to an input terminal 2 is converted to the sawtooth wave by a low-pass filter including a capacitor C.sub.1 and a resistor R.sub.1, and the sawtooth wave is amplified by a differential amplifier including transistor Q.sub.1 and Q.sub.2, which supplies an output signal to a succeeding stage. Numeral 20 denotes a sample and hold circuit. When a voltage which is sufficiently higher than an emitter potential of a transistor Q.sub.3 is applied to an input terminal 1, transistors Q.sub.4 and Q.sub.5 are saturated so that an emitter of the transistor Q.sub.3 is conducted to a base of a transistor Q.sub.6. As a result, a capacitor C.sub.2 is rapidly charged through the transistor Q.sub.4 or discharged through the transistor Q.sub.5 and a resistor 22 to a potential equal to the emitter potential of the transistor Q.sub.3. When the voltage at the input terminal 1 falls, the transistors Q.sub.4 and Q.sub.5 are cut off so that the emitter circuit of the transistor Q.sub.3 is disconnected from the base of the transistor Q.sub.6. Thus, when the voltage at the input terminal 1 is low, there is no discharging path for the charge stored in the capacitor C.sub.2 and the base voltage of the transistor Q.sub.6 is kept constant until the voltage at the input terminal 1 rises subsequently. Namely, when the reference pulse signal is applied to the input terminal 1, portions of the sawtooth wave from the waveform converter circuit 10 are sampled by the reference pulse signal and a sampled voltage is held. In this manner, the ramp wave signal is compared with the pulse signal as is well known in the art.
The output of the sample and hold circuit 20 is applied to an oscillator to be controlled through a lag-lead filter 30 including resistors R.sub.2 and R.sub.3 and a capacitor C.sub.3. A transient response characteristic of the phase control system when the phase of the signal to be phase-compared changes is determined by a time constant of the filter 30.
The sample and hold circuit described above requires a relatively large capacitance for the capacitor C.sub.2 for sampling and holding, and such a capacitor must be mounted externally of the integrated circuit because it cannot be implemented by an on-chip capacitor. As a result, the integrated circuit requires additional lead terminals for the connection with the capacitor. Since the number of lead terminals largely affects the cost of the integrated circuit as is well known, it is necessary to reduce the number of terminals as much as possible.
As an example of the phase comparator circuit which does not need additional lead terminals, a circuit which uses a current Miller circuit as shown in FIG. 2 has been proposed. In FIG. 2, a signal to be phase-compared is applied to the terminal 2 while a reference pulse signal is applied to the terminal 1. Like in the previous example, the resistor R.sub.1 and the capacitor C.sub.1 constitute the low-pass filter for converting the signal to be phase-compared which is applied to the terminal 2 to the sawtooth wave. The sawtooth wave signal, which may be in the form of a waveform shown in FIG. 3a, is applied to a transistor Q.sub.8 of a differential amplifier including the transistors Q.sub.8 and Q.sub.9. The reference pulse signal, which may be in the form of a waveform shown in FIG. 3b, is applied to a base of a transistor Q.sub.12, which is a current source for the differential amplifier, so that the current source is turned on and off in response to the pulse signal. The arrangement of transistors Q.sub.10 and Q.sub.11 functions such that a collector current of the transistor Q.sub.11 is identical to a collector current of the transistor Q.sub.10 and hence a collector current of the transistor Q.sub.8. As a result, a differential current between the collector currents of the transistors Q.sub.9 and Q.sub.8 flows to a path leading to a terminal 4. Thus, when the signals shown in FIGS. 3a and 3b are applied, the differential current between the collector currents of the transistors Q.sub.8 and Q.sub.9 is produced at the terminal 4 only in the on-period of the transistor Q.sub.12, as shown in FIG. 3C. This differential current is supplied to a load circuit including a reference voltage source E, resistors R.sub.4 and R.sub.5 and capacitors C.sub.4 and C.sub.5, and a voltage is developed therein. The reference voltage source E is V.sub.0 when a mean current value of the current waveform shown in FIG. 3C is zero, and it is higher or lower than Vo when the mean current value is positive or negative.
As is seen from FIG. 2, the discharge paths through the resistors R.sub.4 and R.sub.5 always exist for the capacitors C.sub.4 and C.sub.5. Consequently, when the output voltage is different from Vo, the charges stored in the capacitors C.sub.4 and C.sub.5 are discharged through the resistors R.sub.4 and R.sub.5 or they are charged by the reference voltage source E so that the output voltage gradually approaches the reference voltage V.sub.0 in any case. Thus, the circuit operates in a stable manner such that the charge discharged when the level of the reference pulse signal shown in FIG. 3b is low is supplemented during the duration of the high level or the application of the pulse, and the circuit produces an output voltage as shown in FIG. 3d. As seen from the waveform chart, an output D.C. voltage V.sub.1 at the rise of the reference pulse signal (FIG. 3b) is different from an output D.C. voltage V.sub.2 immediately before the fall of the reference pulse signal. As a result, the frequency fo of the oscillator which is controlled by the output D.C. voltage changes from time to time, although the change is slight, with the mean value of the oscillation frequency fo being equal to the multiple of the reference frequency N.multidot.fr. It is theoretically possible to avoid a practical problem caused by the change (hereinafter referred to as a sag) of the D.C. voltage by increasing the capacitances of the capacitors C.sub.4 and C.sub.5 of the low pass filter, but in such a case it is unavoidable that the oscillation frequency always changes because a frequency pull-in range of the automatic frequency control system is narrowed.